1. Field of the Invention
The present invention relates to an ESD protection device and particularly to an ESD protection device for input signals with voltage level higher than VDD or lower than VSS.
2. Description of the Prior Art
ESD protection is one of the main reliability concerns for IC products, especially when scaled down into the deep submicron regime, and the thinner gate oxide of the MOS become more vulnerable to ESD stress. For general industrial specification, the input and output pins of IC products have to sustain HBM (Human Body Model) ESD stress over 2000V and MM (Machine Model) ESD stress over 200V. Therefore, ESD protection circuits must be disposed around the input and output (I/O) pads of the IC.
FIGS. 1˜3 are diagrams showing three traditional ESD protection devices.
In FIG. 1, the ESD protection device 1 includes two diodes 11 and 12 connected between the input pad 13 and the power supply VDD, and input pad 13 and the power supply VSS, respectively. The diode 11 is turned on by a positive ESD pulse across the input pad 13 that flows therefrom to the power supply VDD rather than to the internal circuit 14. Similarly, diode 12 is turned on by a negative ESD pulse across the input pad 13 that flows therefrom to the power supply VSS rather than to the internal circuit 14.
In FIG. 2, the ESD protection device 2 includes a P-type transistor 21 and N-type transistor 22. Operations of the ESD protection devices 1 and 2 are similar. The transistors 21 and 22 are turned on by a positive and negative ESD pulse across the input pad 23 that flows therefrom to the power supply VDD and VSS, respectively. This protects the internal circuit 24 from damage by ESD.
In FIG. 3, the ESD protection device 3 includes a field-oxide NMOS 31, a N-type transistor 32 and a resistor R. The field-oxide NMOS 31 and the N-type transistor 32 provide an ESD path from the input pad 33 to the power supply VSS, which prevents the ESD current from flowing to the internal circuit 34.
Generally speaking, the highest and minimum voltage levels of the input signals of integrated circuits are between the power supply voltages VDD and VSS. However, with the advance of the CMOS manufacturing process, ICs derived from different processes operate at different voltages. For example, the ICs derived from a 0.5 μm CMOS process operate at VDD of 5V, while those derived from a 0.18 μm CMOS process operate at VDD of 1.8V. On a single circuit board, there may be several ICs providing different functions and having I/O pads electrically connected with each other. Thus, each IC may receive I/O signals with different high and low voltage levels. For example, an IC using VDD of 1.8 or 3.3V may receive signals having a high voltage level of 5V output from another IC. This results in an input signal level higher than VDD. Similarly, some situations may cause an input signal lower than VSS. Moreover, in some ICs for network communication, such as ICs receiving signals from a remote device through connection lines, there may be input signals with voltage levels higher than VDD and lower than VSS. The previously described traditional ESD protection devices do not apply to an IC receiving input signals with voltage levels higher than VDD or lower than VSS since they induce leakage currents.
FIGS. 4˜6 are diagrams showing three traditional ESD protection devices applicable to ICs receiving input signals with voltage levels higher than VDD or lower than VSS.
The ESD protection device shown in FIG. 4 is applicable to ICs receiving input signals with voltage levels higher than VDD. The PMOS transistor 41 has a gate connected to a gate voltage tracking circuit 42, a source connected to the power supply VDD, a drain connected to the input pad 43 and a bulk connected to a floating N well (not shown). The gate voltage tracking circuit 42 is connected with the pad 43 and the power supply VDD. The cascaded transistors 44 and 45 are connected between the pad 43 and the power supply VSS. The gates of NMOS transistors 44 and 45 are connected to the power supply VDD and VSS respectively. Although this circuit provides ESD protection for ICs receiving input signals with voltage levels higher than VDD, the ICs are easily damaged by ESD due to low ESD performance.
In FIG. 5, the ESD protection device is applicable to ICs receiving input signals with voltage levels lower than VSS. It includes a PNP bipolar junction transistor 51, a silicon controlled rectifier 52 and a PMOS transistor 54. Although this circuit provides ESD protection for ICs receiving input signals with voltage levels lower than VSS, the N well 521 is floated to prevent forward bias of the parasitic diode formed by the junction between the P substrate 522 and N well 521, which makes the silicon controlled rectifier 52 easy to be unintentionally triggered on. This results in latch-up of the circuit.
In FIG. 6, the ESD protection device is applicable to ICs receiving input signals with voltage levels higher than VDD and lower than VSS. It includes a PNP bipolar junction transistor 61 connected between the input pad 63 and the power supply VSS, a silicon controlled rectifier 62 connected between the input pad 63 and the power supply VSS. Similarly to the ESD protection device shown in FIG. 5, although this circuit provides ESD protection for ICs receiving input signals with voltage levels higher than VDD and lower than VSS, the N well 621 is also floated, which makes the silicon controlled rectifier 62 easy to be unintentionally triggered on. This results in latch-up of the circuit.